Digital communication equipment is used in a wide variety of devices for the transmission of digital information. Such information includes numerical data in computers and digital encodings of voice in telecommunications systems.
In the course of transmission of digital signals from a transmitter to a receiver, the digital signals tend to become degraded. Degradation may involve loss of overall strength of the signal, and loss of definition of the pulse edges: at the time of sending, the pulse edges typically rise and fall sharply with respect to the overall pulse length giving a cleanly defined shape to the pulse whilst, at the receiver, the rate of rise and fall of the pulses tends to decrease resulting in less sharply defined pulses. In order to correct for these degradations, it is common practice to regenerate the original digital signal from the distorted one at the receiving end of a digital communication link. The regenerated signal may then be retransmitted along a further transmission link or be further processed locally.
To regenerate a received signal, typically, in the receiver the received data signal (the data signal) is processed synchronously relative to a local clock signal (the clock signal). The amplitude of the data signal is not sampled near the degraded edges of the received data pulses which would lead to incorrect interpretation of the signal. Not only can the data arrive significantly out of phase with the local clock, but minor variations in the frequency of the clock and of the data mean that the phase difference may vary over time. This means that it is necessary not only to identify the phase difference between clock signal and data signal when the data signal is first detected, but also to monitor the phase difference continually while the data signal is being received.
By continually monitoring the difference in phase between the data and the clock, it is possible to adjust the arrival time of either the data or the clock (or both) in order to keep the phase difference within acceptable limits. One means of achieving this effect is to incorporate a variable-delay buffer in the data path or clock path (or both) and adjust the buffer length by means of a feedback circuit dependent upon the perceived phase difference between the two signals at a later point in the circuit. For example, if the data appears to lag behind the clock, either the delay in the clock signal path may be increased or that in the data signal path may be decreased.
A clock-to-data phase detector is a device which takes as two of its inputs a data signal and a clock signal and generates signals giving information about the phase difference between the data signal and clock signal. A known means of representing the phase difference information is by means of a pair of signals: the first signal (the phase signal) comprises a component which represents the phase difference and a further component which represents the variations in the number of edges occurring in the data; the second signal (the reference signal) represents only the latter variation. Subsequent subtraction of the reference signal from the phase signal gives a signal (the phase difference signal) representing only the difference in phase.
Typical existing clock-to-data phase detectors generate a phase difference signal whose pulse duration varies between 0 and 1 clock periods. A problem with existing clock-to-data phase detectors is that non-linearities in the generated phase difference signal occur when the bit rise and fall intervals of the phase difference signal are large relative to the bit period of said data signal. Pulse rise and fall durations are determined by the silicon components used to output the signal. Pulse durations in excess of 0.5 clock periods typically vary linearly with the phase difference of the received data signal. However, as the duration of pulses in the phase difference signal approaches zero so the proportion of the pulse length affected by the rise and fall intervals increases until the rise and fall intervals dominate. Where the rise and fall intervals dominate, pulse durations in the phase difference signal cease to vary linearly with the phase difference of the received data signal. This problem is serious where the data signal bit rate is high relative to the speed at which the phase detector can operate. At high bit rates, for example 10 Gbit/s, the phase detector speed can be constrained by current silicon fabrication technology limits.
A further problem arises in phase detectors employing bistables, since each bistable device introduces a propagation delay to the signal passing through it and this delay may vary according to ambient temperature and power supply voltage. Differences in the total delay introduced along distinct paths within a detector can give rise to variations in the relative phase of signals arriving at each subsequent component within the detector. It is known [from C. R. Hogge, "A Self Correcting Clock Recovery Circuit", Journal of Lightwave Technology, Vol. LT-3, No. 6, December 1985] to generate a phase difference signal employing circuitry constructed using silicon components, whilst at the same time generating a reference signal by employing a fixed delay introduced by means of a delay line implemented by means of, for example, a fixed length of coaxial cable or printed circuit board track. However such delay lines do not exhibit the same characteristics with respect to temperature and power supply voltage as do the silicon components and this leads to variations in the relative phase between the phase signal and the reference signal.
Whilst it is known to construct a clock-to-clock phase detector which provides a linear phase signal, such a mechanism relies on the regular arrival of pulses in both clock signals. In the case of a clock-to-data phase detector, pulses in the data generally arrive at variable intervals so that such clock-to-clock phase detector methods are not applicable.
Regeneration can be achieved by applying thresholding and limiting to the received signal, followed by retiming. Where the data signal arrives at high frequencies or over long distances, it is conventionally retimed using a clock recovered from the data signal.
Where the data arrives continuously from a single transmitter, the threshold and phase values can vary over time, but such variation is generally, but not always, gradual. In cases where data arrives in bursts however and particularly, but not exclusively, where successive bursts originate from distinct transmitters, the threshold and phase values can vary enormously between bursts. This in addition to the variation over time within each burst.
Where the maximum burst length and frequency deviation within a burst can be limited, it is known [from Wong & Sitch: "A 10 Gb/s ATM Data Synchronizer", IEEE Journal of Solid State Circuits, Vol. 31 No. 109, October 1996] to construct a data synchroniser to resynchronise the received data with the receiver's clock: data transitions of the incoming signal are compared with clock transitions and an error signal is generated if rising and falling transition edges of the data are either both late or both early with respect to the receiver's clock; the error signal so generated is used to adjust the length of a variable length delay buffer present in the data path or clock signal path, thereby effectively bringing the two signals back into alignment.
Existing systems minimise modification of the data signal by adjusting the receiver's clock signal to match the data instead.
It is also known to construct a re-timing circuit taking as input a data signal to be retimed and a clock signal, and providing as output a retimed copy of the received data signal. This circuit may be constructed, for example, using a single D-type bistable.